1. Field of the Invention
The present invention relates to a ferroelectric memory, which is a semiconductor data-storage device that employs capacitors having ferroelectric material sandwiched between two electrodes.
2. Description of the Prior Art
FIG. 2 shows a circuit diagram of a conventional ferroelectric memory. In FIG. 2, WL-h (h=1, . . . , m) represents a word line; CL-i (i=1, . . . , n) represents a column line; PL-h represents a plate line; BL-i1, BL-i1', BL-i2, and BL-i2' represent bit lines; I/O-1 and I/O-2 represent data input/output lines; C-hi1, C-hi1', C-hi2, and C-hi2' represent capacitors having ferroelectric material sandwiched between two electrodes (hereafter referred to as "ferroelectric capacitors"); T-hi1, T-hi1', T-hi2, T-hi2', T-i1, and T-i2 represent n-channel MOS field-effect transistors (hereafter referred to simply as "MOS transistors"); SA-i1 and SA-i2 represent sense amplifiers; and ADD-hi represents the address of the intersection between the h-th row and the i-th column.
These elements are interconnected as follows. The ferroelectric capacitors C-hi1, C-hi1', C-hi2, and C-hi2' have one end connected through the drain-source channel of the MOS transistors T-hi1, T-hi1', T-hi2, and T-hi2' to the bit lines BL-i1, L-i1', BL-i2, and BL-i2', respectively, and have the other end connected to the plate line PL-h. The gates of the MOS transistors T-hi1, T-hi1', T-hi2, and T-hi2' are connected to the word line WL-h.
The bit lines BL-i1 and BL-i1' are connected to one end of the sense amplifier SA-i1, and the bit lines BL-i2 and BL-i2' are connected to one end of the sense amplifier SA-i2. The sense amplifiers SA-i1 and SA-i2 have their other end connected through the drain-source channel of the MOS transistors T-i1 and T-i2 to the data input/output lines I/O-1 and I/O-2, respectively.
Thus, the address ADD-hi of the intersection between the h-th row and the i-th column points to a part of the ferroelectric memory that consists of four ferroelectric capacitors C-hi1, C-hi1', C-hi2, and C-hi2' and four MOS transistors T-hi1, T-hi1', T-hi2, and T-hi2'.
Here, a brief description will be given as to the polarization of a ferroelectric capacitor. As FIG. 3 shows, the relationship between the voltage applied to a ferroelectric capacitor and the state (i.e. the direction and degree) of polarization it exhibits describes a hysteresis loop. Accordingly, even when the applied voltage returns to zero, a certain degree of polarization remains stably (P3 and P4 in FIG. 3). For example, when the applied voltage varies from a sufficiently high positive voltage to zero, the state of polarization shifts from P1 to P3 of FIG. 3; when the applied voltage varies from a sufficiently high negative voltage to zero, the state of polarization shifts from P2 to P4 of FIG. 3. Note that, in the following descriptions, the symbols P1, P2, P3, and P4 invariably refer to those shown in FIG. 3.
A ferroelectric memory exploits this change in the state of polarization of a ferroelectric capacitor between P3 and P4 in order to store therein a binary digit, namely "1" or "0". For example, the state of polarization at P3 is used to represent "0", and the state of polarization at P4 is used to represent "1". Accordingly, a ferroelectric memory is a nonvolatile memory that can hold the data stored therein even while it is not receiving electric power.
The ferroelectric memory is composed of so-called 2T2C-type memory cells. That is, two ferroelectric capacitors C-hix and C-hix' and two MOS transistors T-hix and T-hix' (where x=1, 2) make up one memory cell. And two memory cells make up one address ADD-hi, so that two bits of data can be held at one address.
The writing of data is performed as follows. Prior to the writing of data, the voltages on all word lines WL-h, all column lines CL-i, and all plate lines PL-h drop to a low level, and all sense amplifiers SA-h1 and SA-h2 are activated. Then, for example in a case where two bits of data "1, 0" are going to be written to the address ADD-11 that points to the intersection between the first row and the first column, the word line WL-1 and the column line CL-1 rise to a high level.
As a result, the MOS transistors T-1ix and T-1ix' turn on, connecting the ferroelectric capacitors C-1ix and C-1ix' to the bit lines BL-ix and BL-ix', and the MOS transistor T-1x turns on, connecting the sense amplifier SA-1x to the data input/output line I/O-x. Eventually, only the ferroelectric capacitors C-11x and C-11x', which make up one of the memory cells that constitute the address ADD-11, are connected between the plate line PL-1 and the data input/output line I/O-x (hereafter, this state of an address will be referred to as its "selected" state).
Here, the sense amplifier SA-ix is an amplifier whose input/output direction can be switched in accordance with a control signal fed thereto from outside, and it is additionally provided with a latching function for temporarily holding data. Specifically, during the writing of data, the sense amplifier SA-ix amplifies the voltage on the data input/output line I/O-x, and outputs the amplified voltage as it is to the bit line BL-ix and after inverting it to the bit line BL-ix'. On the other hand, during the reading of data, the sense amplifier SA-ix compares the potential difference between the bit lines BL-ix and BL-ix' with a reference voltage, and, in accordance with the result of the comparison, outputs a high-level or low-level voltage to the data input/output line I/O-x; that is, it judges whether the potential difference between the bit lines BL-ix and BL-ix' corresponds to a binary "1" or "0".
As a result, in the case under discussion, where it is assumed that two bits of data "1, 0" are written, when the data input/output line I/O-1 rises to a high level, which corresponds to a binary "1", and the data input/output line I/O-2 drops to a low level, which corresponds to a binary "0", the input of the sense amplifier SA-11 rises to a high level, causing the voltage on the bit line BL-11 to rise to a high level and the voltage on the bit line BL-11' to drop to a low level, and the input of the sense amplifier SA-12 drops to a low level, causing the voltage on the bit line BL-12 to drop to a low level and the voltage on the bit line BL-12' to rise to a high level.
As a result, the ferroelectric capacitors C-111 and C-112' receive a voltage such that their bit line (BL-11 and BL-12') side becomes positive and their plate line (PL-1) side becomes negative (hereafter referred to as "receiving a negative voltage"), and therefore they shift their state of polarization to P2. On the other hand, the ferroelectric capacitors C-111' and C-112 receive a zero voltage, and therefore they shift their state of polarization to P3 or P4 depending on their previous state of polarization.
Next, when the voltage on the plate line PL-1 rises to a high level, the ferroelectric capacitors C-111 and C-112' receive a zero voltage, and therefore they shift their state of polarization from P2 to P4; on the other hand, the ferroelectric capacitors C-111' and C-112 receive a voltage such that their plate line (PL-1) side becomes positive and their bit line (BL-11' and BL-12) side becomes negative (hereafter referred to as "receiving a positive voltage"), and therefore they shift their state of polarization from P3 or P4 to P1.
Next, when the voltage on the plate line PL-1 drops to a low level, the ferroelectric capacitors C-111 and C-112' receive a negative voltage, and therefore they shift their state of polarization from P4 to P2; on the other hand, the ferroelectric capacitors C-111' and C-112 receive a zero voltage, and therefore they shift their state of polarization from P1 to P3.
Next, when the voltages on the word line WL-1 and the column line CL-1 drop to a low level, the MOS transistors T-1ix and T-1ix' turn off, disconnecting the ferroelectric capacitors C-1ix and C-1ix' from the bit lines BL-ix and BL-ix', respectively, and the MOS transistor T-1x turns off, disconnecting the sense amplifier SA-1x from the data input/output line I/O-x (i.e. the address ADD-11 returns to its "non-selected" state).
This is the end of the process of writing two bits of data "1, 0" to the address ADD-11 that points to the intersection between the first row and the first column. At this time, the state of polarization of the ferroelectric capacitors C-111 and C-111' is at P4 and P3, respectively, and the state of polarization of the ferroelectric capacitors C-112 and C-112' is at P3 and P4, respectively. Note that, although the state of polarization of the ferroelectric capacitors C-111 and C-112' is at P2 immediately after the writing of the two-bit data "1, 0" to the address ADD-11, a leak current flowing through the MOS transistors make their state of polarization eventually settle to P4.
In short, a binary "1" is represented by making two adjacent ferroelectric capacitors C-hix and C-hix' shift their state of polarization to P4 and P3, respectively, and a binary "0" is represented by making two adjacent ferroelectric capacitors C-hix and C-hix' shift their state of polarization to P3 and P4, respectively. That is, a binary "1" or "0" is written to a specific address by stabilizing the two ferroelectric capacitors C-hix and C-hix' constituting one memory cell in one of two opposite combinations of different states of polarization for "1" and "0".
The reading of data is performed as follows. Prior to the reading of data, the voltages on all word lines WL-h, all column lines CL-i, and all plate lines PL-h drop to a low level, and all sense amplifiers SA-h1 and SA-h2 are deactivated. Then, for example in a case where data is going to be read from the address ADD-11 that points to the intersection between the first row and the first column, the word line WL-1 and the column line CL-1 rise to a high level, and thus the address ADD-11 is selected.
Next, when the voltage on the plate line PL-1 rises to a high level, the ferroelectric capacitors C-111, C-111', C-112, and C-112' receive a positive voltage, and therefore they shift their state of polarization from P3 or P4 to P1. This causes the ferroelectric capacitors C-111, C-111', C-112, and C-112' to release electric charges, which induce voltages on the bit lines BL-11, BL-11', BL-12, and BL-12' through the wiring capacitance of these bit lines.
The amount of electric charge released from the ferroelectric capacitors C-111, C-111', C-112, and C-112' varies depending on whether their state of polarization is at P3 or P4 before they shift to P1. Specifically, if the state of polarization of a ferroelectric capacitor is at P4 before it shifts to P1, it releases a larger amount of electric charge, and thus induces a higher voltage on a bit line; if the state of polarization of a ferroelectric capacitor is at P3 before it shifts to P1, it releases a smaller amount of electric charge, and thus induces a lower voltage on a bit line.
More specifically, in a case where, out of the two memory cells constituting the address ADD-11 that points to the intersection between the first row and the first column, the one including the ferroelectric capacitors C-111 and C-111' is holding a binary "1" and the other including the ferroelectric capacitors C-112 and C-112' is holding a binary "0", the voltage on the bit line BL-11 is high, and the voltage on the bit line BL-11' is low; on the other hand, the voltage on the bit line BL-12 is low, and the voltage on the bit line BL-12' is high.
Then, the sense amplifier SA-11 is activated, so that it receives the voltages on the bit lines BL-11 and BL-11' and thereby raises the voltage on the data input/output line I/O-1 to a high level, which corresponds to a binary "1"; on the other hand, the sense amplifier SA-12 is also activated, so that it receives the voltages on the bit lines BL-12 and BL-12' and thereby drops the voltage on the data input/output line I/O-2 to a low level, which corresponds to a binary "0".
This marks the end of outputting the two-bit data "1, 0" held at the address ADD-11. Thereafter, the voltages on the plate line PL-1 and the word line WL-1 drop to a low level, and then the voltage on the column line CL-1 drops to a low level. This is the end of the process of data reading.
Here, the voltages that appear on the bit lines during the reading of data are in a range from tens of millivolts to hundreds of millivolts, and therefore the voltage difference between the high level and the low level that appear on the bit lines is considerably small. This makes it difficult, in a ferroelectric memory of the type that uses only one ferroelectric capacitor to hold one bit of data, that is, in a ferroelectric memory composed of so-called 1T1C-type memory cells, to judge whether the voltage appearing on a bit line corresponds to a binary "1" or "0". Thus, with such a ferroelectric memory, there is a high risk that data may be read incorrectly.
By contrast, in a ferroelectric memory composed of 2T2C-type memory cells, it is the difference between the high level and the low level appearing on the bit lines that is used to judge whether a memory cell is holding a binary "1" or "0". This allows the voltage difference between the voltage representing a binary "1" and the voltage representing a binary "0" to be twice as large as in a ferroelectric memory composed of 1T1C-type memory cells, and thus permits more correct reading of data.
After the reading of data from the address ADD-11 that points to the intersection between the first row and the first column, the ferroelectric capacitors C-111, C-111', C-112, and C-112' of that address ADD-11 all shift their state of polarization to P3. This means that, when data is read, the data is erased from the memory cells in which it has been held up to that moment; that is, a ferroelectric memory is a destructive readout (DRO) memory.
Accordingly, after the reading of data, it is necessary to rewrite the data that has been held previously. For this reason, the sense amplifier SA-ix is provided with a latching function, so that, after the reading of data, the sense amplifier SA-ix performs the rewriting of the data that has just been read out.
In the conventional ferroelectric memory described heretofore, when a specific address is accessed, that is, when data is written to or read from, for example, the address ADD-11 that points to the intersection between the first row and the first column, the ferroelectric capacitors C-1ix and C-1ix' that constitute a memory cell at the address ADD-1i get one end connected to the bit lines BL-ix and BL-ix', respectively, and the voltage on the plate line PL-1 undergoes level shifts. Since the ferroelectric capacitors C-1ix and C-1ix' have the other end connected to this plate line PL-1, such access to the address ADD-11 ends in destroying not only the data held at the address ADD-11, but also the data held at all the addresses ADD-1i in the same row as ADD-11. This necessitates that the rewriting of previously held data be performed for all the addresses in the same row as the address that is actually accessed.
Thus, it is necessary to provide each column of addresses with as many sense amplifiers as the number of bits that can be held at one address, and keep all of those sense amplifiers active when one of the addresses associated therewith is accessed. Accordingly, the conventional ferroelectric memory requires an unduly large circuit area and consumes an unduly large amount of electric current.
Moreover, since many ferroelectric capacitors C-h11, C-h11', C-h12, C-h12', . . . , C-hn1, C-hn1', C-hn2, and C-hn2' are connected to the plate line PL-h, the driving of the plate line Pl-h requires a large-capacity plate line driver (not shown). This cannot be achieved without the use of as many MOS transistors, of which each occupies a large area, as the number of plate lines, and thus further increases the circuit area and the current consumption of the conventional ferroelectric memory.
Furthermore, since the rewriting of data is performed for all the addresses in the same row as the actually accessed address, each address is subjected to data writing an extremely large number of times. As a result, the conventional ferroelectric memory suffers from comparatively low reliability and short working life.